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integrated silicon solution, inc . - www.issi.com 1 rev. a 07/18/2012 copyright ? 2012 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat - est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason - ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is42s32800g is45s32800g features ? clock frequency: 200, 166, 143 mhz ? fully synchronous; all signals referenced to a positive clock edge ? internal bank for hiding row access/precharge ? single power supply: 3.3v + 0.3v ? lvttl interface ? programmable burst length C (1, 2, 4, 8, full page) ? programmable burst sequence: sequential/interleave ? auto refresh (cbr) ? self refresh ? 4096 refresh cycles every 16ms (a2 grade) or 64 ms (commercial, industrial, a1 grade) ? random column address every clock cycle ? programmable cas latency (2, 3 clocks) ? burst read/write and burst read/single write operations capability ? burst termination by burst stop and precharge command options ? package: 90-ball tf-bga ? operating temperature range: commercial (0 o c to +70 o c) industrial (-40 o c to +85 o c) automotive grade, a1 (-40 o c to +85 o c) automotive grade, a2 (-40 o c to +105 o c) overview issi 's 256mb synchronous dram achieves high-speed data transfer using pipeline architecture. all inputs and outputs signals refer to the rising edge of the clock input. the 256mb sdram is organized in 2meg x 32 bit x 4 banks. 8m x 32 256mb synchronous dram august 2012 key timing parameters parameter -5 -6 -7 unit clk cycle time cas latency = 3 5 6 7 ns cas latency = 2 10 10 7.5 ns clk frequency cas latency = 3 200 166 143 mhz cas latency = 2 100 100 133 mhz access time from clock cas latency = 3 4.8 5.4 5.4 ns cas latency = 2 6.5 6.5 5.5 ns address table parameter 8m x 32 confguration 2m x 32 x 4 banks refresh count com./ind. a1 a2 4k / 64ms 4k / 64ms 4k / 16ms row addresses a0 C a11 column addresses a0 C a8 bank address pins ba0, ba1 autoprecharge pins a10/ap
2 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g device overview the 256mb sdram is a high speed cmos, dynamic random-access memory designed to operate in 3.3v v dd and 3.3v v ddq memory systems containing 268,435,456 bits. internally confgured as a quad-bank dram with a synchronous interface. each 67,108,864-bit bank is orga - nized as 4,096 rows by 512 columns by 32 bits. the 256mb sdram includes an auto refresh mode, and a power-saving, power-down mode. all signals are registered on the positive edge of the clock signal, clk. all inputs and outputs are lvttl compatible. the 256mb sdram has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. a self-timed row precharge initiated at the end of the burst sequence is available with the auto precharge function enabled. precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. sdram read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. the registration of an active command begins accesses, followed by a read or write command. the active command in conjunction with address bits registered are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a11 select the row). the read or write commands in conjunction with address bits registered are used to select the starting column location for the burst access. programmable read or write burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option. clk cke cs ras cas we a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 ba1 a10 command decoder & clock genera to r mode register refresh contr oller refresh counter self refresh contro ller ro w address la tch mul tiplexer column address la tch burst counter column address buffer column decoder da ta in buffer da ta out buffer dqm0 - dqm3 dq 0-31 v dd /v ddq v ss /v ss q 12 12 9 12 12 9 32 32 32 32 512 (x 32) 4096 4096 4096 ro w decoder 4096 memor y cell arra y ba nk 0 sense amp i/o ga te bank contr ol logic ro w address buffer a11 4 functional block diagram ( for 2m x 32 x 4 banks)
3 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g pin configuration package code: b 90 ball tf-bga (top view) (8.00 mm x 13.00 mm body, 0.8 mm ball pitch) 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l m n p r dq26 dq28 vssq vssq vddq vs s a4 a7 clk dqm1 vddq vssq vssq dq11 dq13 dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke nc dq8 dq10 dq12 vddq dq15 vs s vssq dq25 dq30 nc a3 a6 nc a9 nc vs s dq9 dq14 vssq vs s vdd vddq dq22 dq17 nc a2 a10 nc ba 0 cas vdd dq6 dq1 vddq vdd dq23 vssq dq20 dq18 dq16 dqm2 a0 ba 1 cs we dq7 dq5 dq3 vssq dq0 dq21 dq19 vddq vddq vssq vdd a1 a11 ras dqm0 vssq vddq vddq dq4 dq2 pin descriptions a0-a11 row address input a0-a8 column address input ba0, ba1 bank select address dq0 to dq31 data i/o clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command we write enable dqm0-dqm3 x32 input/output mask v power vss ground v power supply for i/o pin vss ground for i/o pin nc no connection
4 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g pin functions symbol type function (in detail) a0-a11 input pin address inputs: a0-a11 are sampled during the active command (row-address a0-a11) and read/write command (column address a0-a8), with a10 defning auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. ba0, ba1 input pin bank select address: ba0 and ba1 defnes which bank the active, read, write or precharge command is being applied. cas input pin cas , in conjunction with the ras and we , forms the device command. see the "command truth table" for details on device commands. cke input pin the cke input determines whether the clk input is enabled. the next rising edge of the clk signal will be valid when is cke high and invalid when low. when cke is low, the device will be in either power-down mode, clock suspend mode, or self refresh mode. cke is an asynchronous i nput. clk input pin clk is the master clock input for this device. except for cke, all inputs to this device are acquired in synchronization with the rising edge of this pin. cs input pin the cs input determines whether command input is enabled within the device. command input is enabled when cs is low, and disabled with cs is high. the device remains in the previous state when cs is high. dqm0-dqm3 input pin dqm0 - dqm3 control the four bytes of the i/o buffers (dq0-dq31). in read mode, dqmn control the output buffer. when dqmn is low, the corresponding buf - fer byte is enabled, and when high, disabled. the outputs go to the high imped - ance state whendqmn is high. this function corresponds to oe in conventional drams. in write mode, dqmn control the input buffer. when dqmn is low, the corresponding buffer byte is enabled, and data can be written to the device. when dqmn is high, input data is masked and cannot be written to the device. dq0-dq31 input/output pin data on the data bus is latched on these pins during write commands, and buffered after read commands. ras input pin ras , in conjunction with cas and we , forms the device command. see the "com - mand truth table" item for details on device commands. we input pin we , in conjunction with ras and cas , forms the device command. see the "com - mand truth table" item for details on device commands. v ddq power supply pin v ddq is the output buffer power supply. v dd power supply pin v dd is the device internal power supply. v ssq power supply pin v ssq is the output buffer ground. v ss power supply pin v ss is the device internal ground.
5 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g general description read the read command selects the bank from ba0, ba1 inputs and starts a burst read access to an active row. inputs a0-a8 provides the starting column location. when a10 is high, this command functions as an auto precharge command. when the auto precharge is selected, the row being accessed will be precharged at the end of the read burst. the row will remain open for subsequent accesses when auto precharge is not selected. dqs read data is subject to the logic level on the dqm inputs two clocks earlier. when a given dqm signal was registered high, the corresponding dqs will be high-z two clocks later. dqs will provide valid data when the dqm signal was registered low. write a burst write access to an active row is initiated with the write command. ba0, ba1 inputs selects the bank, and the starting column location is provided by inputs a0-a8. whether or not auto-precharge is used is determined by a10. the row being accessed will be precharged at the end of the write burst, if auto precharge is selected. if auto precharge is not selected, the row will remain open for subsequent accesses. a memory array is written with corresponding input data on dqs and dqm input logic level appearing at the same time. data will be written to memory when dqm signal is low. when dqm is high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. ba0, ba1 can be used to select which bank is precharged or they are treated as dont care. a10 determined whether one or all banks are precharged. after execut - ing this command, the next command for the selected bank(s) is executed after passage of the period t rp , which is the period required for bank precharging. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge the auto precharge function ensures that the pre - charge is initiated at the earliest valid stage within a burst. this function allows for individual-bank precharge without requiring an explicit command. a10 to enable the auto precharge function in conjunction with a specifc read or write command. for each individual read or write command, auto precharge is either enabled or disabled. auto precharge does not apply except in full-page burst mode. upon completion of the read or write burst, a precharge of the bank/row that is addressed is automatically performed. auto refresh command this command executes the auto refresh operation. the row address and bank to be refreshed are automatically generated during this operation. the stipulated period (t rc ) is required for a single refresh operation, and no other com - mands can be executed during this period. this command is executed at least 4096 times for every t ref . during an auto refresh command, address bits are dont care. this command corresponds to cbr auto-refresh. burst terminate the burst terminate command forcibly terminates the burst read and write operations by truncating either fxed-length or full-page bursts and the most recently registered read or write command prior to the burst terminate. command inhibit command inhibit prevents new commands from being executed. operations in progress are not affected, apart from whether the clk signal is enabled no operation when cs is low, the nop command prevents unwanted commands from being registered during idle or wait states. load mode register during the load mode register command the mode register is loaded from a0-a11. this command can only be issued when all banks are idle. active command when the active command is activated, ba0, ba1 inputs selects a bank to be accessed, and the address inputs on a0-a11 selects the row. until a precharge command is issued to the bank, the row remains open for accesses.
6 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g cke dqm function n-1 n u l data write / output enable h l l data mask / output disable h h h upper byte write enable / output enable h l lower byte write enable / output enable h l upper byte write inhibit / output disable h h lower byte write inhibit / output disable h h cke a11 function n C 1 n cs ras cas we ba1 ba0 a10 a9 - a0 device deselect (desl) h h no operation (nop) h l h h h burst stop (bst) h l h h l read h l h l h v v l v read with auto precharge h l h l h v v h v write h l h l l v v l v write with auto precharge h l h l l v v h v bank activate (act) h l l h h v v v v precharge select bank (pre) h l l h l v v l precharge all banks (pall) h l l h l h cbr auto-refresh (ref) h h l l l h self-refresh (self) h l l l l h mode register set (mrs) h l l l l l l l v command truth table dqm truth table note: h=v ih , l=v il x= v ih or v il , v = valid data. note: h=v ih , l=v il x= v ih or v il , v = valid data.
7 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g cke current state /function n C 1 n cs ras cas we address activating clock suspend mode entry h l any clock suspend mode l l clock suspend mode exit l h auto refresh command idle (ref) h h l l l h self refresh entry idle (self) h l l l l h power down entry idle h l self refresh exit l h l h h h l h h power down exit l h note: h=v ih , l=v il x= v ih or v il , v = valid data. cke truth table
8 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g current state cs ras cas we address command action idle h x x x x desl nop or power down (2) l h h h x nop nop or power down (2) l h h l x bst nop or power down l h l h ba, ca, a10 read/reada illegal (3) l h l l a, ca, a10 writ/ writa illegal (3) l l h h ba, ra act row activating l l h l ba, a10 pre/pall nop l l l h x ref/self auto refresh or self-refresh (4) l l l l oc, ba1=l mrs mode register set row active h x x x x desl nop l h h h x nop nop l h h l x bst nop l h l h ba, ca, a10 read/reada begin read (5) l h l l ba, ca, a10 writ/ writa begin write (5) l l h h ba, ra act illegal (3) l l h l ba, a10 pre/pall precharge precharge all banks (6) l l l h x ref/self illegal l l l l oc, ba mrs illegal read h x x x x desl continue burst to end to row active l h h h x nop continue burst to end row row active l h h l x bst burst stop, row active l h l h ba, ca, a10 read/reada terminate burst, begin new read (7) l h l l ba, ca, a10 writ/writa terminate burst, begin write (7,8) l l h h ba, ra act illegal (3) l l h l ba, a10 pre/pall terminate burst precharging l l l h x ref/self illegal l l l l oc, ba mrs illegal write h x x x x desl continue burst to end write recovering l h h h x nop continue burst to end write recovering l h h l x bst burst stop, row active l h l h ba, ca, a10 read/reada terminate burst, start read : determine ap (7,8) l h l l ba, ca, a10 writ/writa terminate burst, new write : determine ap (7) l l h h ba, ra ra act illegal (3) l l h l ba, a10 pre/pall terminate burst precharging (9) l l l h x ref/self illegal l l l l oc, ba mrs illegal functional truth table note: h=v ih , l=v il x= v ih or v il , v = valid data, ba= bank address, ca+column address, ra=row address, oc= op-code
9 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g current state cs ras cas we address command action read with auto h desl continue burst to end, precharge precharging l h h h x nop continue burst to end, precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal (11) l h l l ba, ca, a10 writ/ writa illegal (11) l l h h ba, ra act illegal (3) l l h l ba, a10 pre/pall illegal (11) l l l h ref/self illegal l l l l oc, ba mrs illegal write with auto h desl continue burst to end, write precharge recovering with auto precharge l h h h nop continue burst to end, write recovering with auto precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal (11) l h l l ba, ca, a10 writ/ writa illegal (11) l l h h ba, ra act illegal (3,11) l l h l ba, a10 pre/pall illegal (3,11) l l l h ref/self illegal l l l l oc, ba mrs illegal precharging h desl nop, enter idle after trp l h h h nop nop, enter idle after trp l h h l bst nop, enter idle after trp l h l h ba, ca, a10 read/reada illegal (3) l h l l ba, ca, a10 writ/writa illegal (3) l l h h ba, ra act illegal (3) l l h l ba, a10 pre/pall nop enter idle after trp l l l h ref/self illegal l l l l oc, ba mrs illegal row activating h desl nop, enter bank active after trcd l h h h nop nop, enter bank active after trcd l h h l bst nop, enter bank active after trcd l h l h ba, ca, a10 read/reada illegal (3) l h l l ba, ca, a10 writ/writa illegal (3) l l h h ba, ra act illegal (3,9) l l h l ba, a10 pre/pall illegal (3) l l l h ref/self illegal l l l l oc, ba mrs illegal functional truth table continued: note: h=v ih , l=v il x= v ih or v il , v = valid data, ba= bank address, ca+column address, ra=row address, oc= op-code
10 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g current state cs ras cas we address command action write recovering h desl nop, enter row active after tdpl l h h h nop nop, enter row active after tdpl l h h l bst nop, enter row active after tdpl l h l h ba, ca, a10 read/reada begin read (8) l h l l ba, ca, a10 writ/ writa begin new write l l h h ba, ra act illegal (3) l l h l ba, a10 pre/pall illegal (3) l l l h ref/self illegal l l l l oc, ba mrs illegal write recovering h desl nop, enter precharge after tdpl with auto l h h h nop nop, enter precharge after tdpl precharge l h h l bst nop, enter row active after tdpl l h l h ba, ca, a10 read/reada illegal (3,8,11) l h l l ba, ca, a10 writ/writa illegal (3,11) l l h h ba, ra act illegal (3,11) l l h l ba, a10 pre/pall illegal (3,11) l l l h ref/self illegal l l l l oc, ba mrs illegal refresh h desl nop, enter idle after trc l h h nop/bst nop, enter idle after trc l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/pall illegal l l l h ref/self illegal l l l l oc, ba mrs illegal mode register h desl nop, enter idle after 2 clocks accessing l h h h nop nop, enter idle after 2 clocks l h h l bst illegal l h l ba, ca, a10 read/write illegal l l ba, ra act/pre/pall illegal ref/mrs functional truth table continued: note: h=v ih , l=v il x= v ih or v il , v = valid data, ba= bank address, ca+column address, ra=row address, oc= op-code notes: 1. all entries assume that cke is active (cken-1=cken=h). 2. if both banks are idle, and cke is inactive (low), the device will enter power down mode. all input buffers except cke will be disabled. 3. illegal to bank in specifed states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. if both banks are idle, and cke is inactive (low), the device will enter self-refresh mode. all input buffers except cke will be disabled. 5. illegal if trcd is not satisfed. 6. illegal if tras is not satisfed. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. must mask preceding data which dont satisfy tdpl. 10. illegal if trrd is not satisfed. 11. illegal for single bank, but legal for other banks.
11 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g cke related command truth table (1) cke current state operation n-1 n cs ras cas we address self-refresh (s.r.) invalid, clk (n - 1) would exit s.r. h x x x x x x self-refresh recovery (2) l h h x x x x self-refresh recovery (2) l h l h h x x illegal l h l h l x x illegal l h l l x x x maintain s.r. l l x x x x x self-refresh recovery idle after t rc h h h x x x x idle after t rc h h l h h x x illegal h h l h l x x illegal h h l l x x x begin clock suspend next cycle (5) h l h x x x x begin clock suspend next cycle (5) h l l h h x x illegal h l l h l x x illegal h l l l x x x exit clock suspend next cycle (2) l h x x x x x maintain clock suspend l l x x x x x power-down (p.d.) invalid, clk (n - 1) would exit p.d. h x x x x x exit p.d. --> idle (2) l h x x x x x maintain power down mode l l x x x x x both banks idle refer to operations in operative command table h h h x x x refer to operations in operative command table h h l h x x refer to operations in operative command table h h l l h x auto-refresh h h l l l h x refer to operations in operative command table h h l l l l op - code refer to operations in operative command table h l h x x x refer to operations in operative command table h l l h x x refer to operations in operative command table h l l l h x self-refresh (3) h l l l l h x refer to operations in operative command table h l l l l l op - code power-down (3) l x x x x x x any state refer to operations in operative command table h h x x x x x other than begin clock suspend next cycle (4) h l x x x x x listed above exit clock suspend next cycle l h x x x x x maintain clock suspend l l x x x x x notes: 1. h : high level, l : low level, x : high or low level (dont care). 2. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfed before any command other than exit. 3. power down and self refresh can be entered only from the both banks idle state. 4. must be legal command as defned in operative command table. 5. illegal if t xsr is not satisfed.
12 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g mode register set idle self refresh cbr (auto) refresh row active active power down power down write write suspend read read suspend writea suspend writea reada reada suspend power on precharge automatic sequenc e manual input self self exit ref mrs act cke cke cke cke bst read write write precharge rre (prec harge termination) pre (precharg e termination) write with auto precharge read with auto prech arge read write bst cke cke cke cke cke cke cke cke read state diagram
13 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g absolute maximum ratings (1) symbol parameters rating unit v dd max maximum supply voltage -0.5 to +4.6 v v ddq max maximum supply voltage for output buffer -0.5 to +4.6 v v in input voltage -0.5 to v dd + 0.5 v v out output voltage -1.0 to v ddq + 0.5 v p d max allowable power dissipation 1 w i cs o utput shorted current 50 ma t opr o perating temperature com. 0 to +70 c ind. -40 to +85 a1 -40 to +85 a2 -40 to +105 t stg storage temperature -65 to +150 c dc recommended operating conditions (t a = 0 o c to +70 o c for commercial grade. t a = -40 o c to +85 o c for industrial and a1 grade. t a = -40 o c to +105 o c for a2 grade.) symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ddq i/o supply voltage 3.0 3.3 3.6 v v ih (1) input high voltage 2.0 v ddq + 0.3 v v il (2) input low voltage -0.3 +0.8 v capacitance characteristics (at t a = 0 to +25c, v dd = v ddq = 3.3 0.3v) symbol parameter min. max. unit -6 -7 c in 1 input capacitance: clk 2.5 3.5 4.0 pf c in 2 input capacitance:all other input pins 2.5 3.8 5.0 pf c i / o data input/output capacitance:i/os 4.0 6.5 6.5 pf note: 1. v ih (max) = v ddq +1.2v ( pulse width < 3 ns ). 2. v il (min) = - 1.2v ( pulse width < 3 ns ). 3. all voltages are referenced to vss. notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all voltages are referenced to vss. package substrate theta-ja (airfow = 0m/s) theta-ja (airfow = 1m/s) theta-ja (airfow = 2m/s) theta-jc units bga(90) 4-layer 36.0 32.7 30.6 6.7 c/w thermal resistance
14 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g dc electrical characteristics 1 (3) (recommended operation conditions unless otherwise noted.) symbol parameter test condition -5 -6 -7 unit i dd 1 (1) operating current one bank active, cl = 3, bl = 1, 190 180 175 ma t clk = t clk (min), t rc = t rc (min) i dd 2 p precharge standby current cke v il ( max ), t ck = 15ns 4 4 4 ma (in power-down mode) i dd 2 ps precharge standby current cke v il ( max ), clk v il ( max ) 4 4 4 ma (in power-down mode) i dd 2 n (2) precharge standby current cs v dd - 0.2v, cke v ih ( min ) 25 25 25 ma (in non power-down mode) t ck = 15ns i dd 2 ns precharge standby current cs v dd - 0.2v, cke v ih ( min ) or 15 15 15 ma (in non power-down mode) cke v il ( max ), all inputs stable i dd 3 p active standby current cke v il ( max ), t ck = 15ns 10 10 10 ma (power-down mode) i dd 3 ps active standby current cke v il ( max ), clk v il ( max ) 10 10 10 ma (power-down mode) i dd 3 n (2) active standby current cs v dd - 0.2v, cke v ih ( min ) 35 35 35 ma (in non power-down mode) t ck = 15ns i dd 3 ns active standby current cs v dd - 0.2v, cke v ih ( min ) or 30 30 30 ma (in non power-down mode) cke v il ( max ), all inputs stable i dd 4 operating current all banks active, bl = 4, cl = 3, 250 230 210 ma t ck = t ck (min) i dd 5 auto-refresh current t rc = t rc (min), t clk = t clk (min) 260 250 240 ma i dd 6 self-refresh current cke 0.2v 5 5 5 ma notes: 1. i dd ( max ) is specifed at the output open condition. 2. input signals are changed one time during 30ns. 3. all values applicable for operation for t a 85 c. for a2 temperature grade with t a > 85 c: idd1 and idd4 are derated to 5% above these values; idd3ns is derated to 30% above these values. dc electrical characteristics 2 (recommended operation conditions unless otherwise noted.) symbol parameter test condition min max unit i il input leakage current 0v vin v dd , with pins other than -10 10 a the tested pin at 0v i ol output leakage current output is disabled, 0v vout v dd , -10 10 a v oh output high voltage level i oh = -2ma 2.4 v v ol output low voltage level i ol = 2ma 0.4 v
15 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g ac electrical characteristics (1,2,3,4) -5 -6 -7 symb ol parameter min. max. min. max. min. max. units t ck 3 clock cycle time cas latency = 3 5 6 7 ns t ck 2 cas latency = 2 10 10 7.5 ns t ac 3 access time from clk cas latency = 3 4.8 5.4 5.4 ns t ac 2 cas latency = 2 6.5 6.5 5.5 ns t ch clk high level width 2.5 2.5 2.5 ns t cl clk low level width 2.5 2.5 2.5 ns t oh 3 output data hold time cas latency = 3 2.7 2.7 2.7 ns t oh 2 cas latency = 2 2.7 2.7 2.7 ns t lz output low impedance time 0 0 0 ns t hz output high impedance time 2.7 4.8 2.7 5.4 2.7 5.4 ns t ds input data setup time (2) 1.5 1.5 1.5 ns t dh input data hold time (2) 1.0 1.0 1.0 ns t as address setup time (2) 1.5 1.5 1.5 ns t ah address hold time (2) 1.0 1.0 1.0 ns t cks cke setup time (2) 1.5 1.5 1.5 ns t ckh cke hold time (2) 1.0 1.0 1.0 ns t cms command setup time ( cs , ras , cas , we , dqm) (2) 1.5 1.5 1.5 ns t cmh command hold time ( cs , ras , cas , we , dqm) (2) 1.0 1.0 1.0 ns t rc command period (ref to ref / act to act) 55 60 67.5 ns t ras command period (act to pre) 40 100k 42 100k 45 100k ns t rp command period (pre to act) 15 18 15 ns t rcd active command to read / write command delay time 15 18 15 ns t rrd command period (act [0] to act[1]) 10 12 14 ns t dpl input data to precharge 10 12 14 ns command delay time t dal input data to active / refresh 25 30 30 ns command delay time (during auto-precharge) t mrd mode register program time 10 12 14 ns t dde power down exit setup time 5 6 7 ns t xsr self-refresh exit time (5) 70 70 70 ns t t transition time 0.3 1.2 0.3 1.2 0.3 1.2 ns t ref refresh cycle time (4096) t a 70 o c com., ind., a1, a2 64 64 64 ms t a 85 o c ind., a1, a2 64 64 64 ms t a > 85 o c a2 16 16 ms notes: 1. the power-on sequence must be executed before starting memory operation. 2. m easured with t t = 1 ns. if clock rising time is longer than 1ns, (t t /2 - 0.5) ns should be added to the parameter. 3. the reference level is 1.4v when measuring input signal timing. rise and fall times are measured between v ih (min.) and v il (max). 4. use recommended operation conditions. 5. self-refresh mode is not supported for a2 grade with t a > +85 o c.
16 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g operating frequency / latency relationships symbol parameter units clock cycle time 5 6 7 7 ns operating frequency 200 166 143 133 mhz t cac cas latency 3 3 3 2 cycle t rcd active command to read/write command delay time 3 3 3 2 cycle t rac ras latency (t rcd + t cac ) cas latency = 3 6 6 6 cycle cas latency = 2 4 t rc command period (ref to ref / act to act) 11 10 10 9 cycle t ras command period (act to pre) 8 7 7 6 cycle t rp command period (pre to act) 3 3 3 2 cycle t rrd command period (act[0] to act [1]) 2 2 2 2 cycle t ccd column command delay time 1 1 1 1 cycle (read, reada, writ, writa) t dpl input data to precharge command delay time 2 2 2 2 cycle t dal input data to active/refresh command delay time 5 5 5 4 cycle (during auto-precharge) t rbd burst stop command to output in high-z delay time cas latency = 3 3 3 3 cycle (read) cas latency = 2 2 t wbd burst stop command to input in invalid delay time 0 0 0 0 cycle (write) t rql precharge command to output in high-z delay time cas latency = 3 3 3 3 cycle (read) cas latency = 2 2 t wdl precharge command to input in invalid delay time 0 0 0 0 cycle (write) t pql last output to auto-precharge start time (read) cas latency = 3 -2 -2 -2 cycle cas latency = 2 -1 t qmd dqm to output delay time (read) 2 2 2 2 cycle t dmd dqm to input delay time (write) 0 0 0 0 cycle t mrd mode register set to command delay time 2 2 2 2 cycle
17 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g ac test conditions input load output load output z = 50 50 pf 1.4v 50 3.0v 1.4v 0v clk input output t ch t cmh t ac t oh t cms t ck t cl 3.0v 1.4v 1.4v 1.4v 0v ac test conditions parameter rating ac input levels 0v to 3.0v input rise and fall times 1 ns input timing reference level 1.4v output timing measurement reference level 1.4v
18 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g functional description read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an ac - tive command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-a11 select the row) . the address bits a0-a8 registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initial - ized. the following sections provide detailed information covering device initialization, register defnition, command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefned manner. the 256m sdram is initialized after the power is applied to v dd and v ddq (simultaneously) and the clock is stable with dqm high and cke high. a 100s delay is required prior to issuing any command other than a command inhibit or a nop . the command inhibit or nop may be applied during the 100s period and should continue at least through the end of the period. with at least one command inhibit or nop command having been applied, a precharge command should be applied once the 100s delay has been satisfed. all banks must be precharged. this will leave all banks in an idle state after which at least two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is then ready for mode register programming. the mode register should be loaded prior to applying any operational command because it will power up in an unknown state.
19 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g initialize and load mode register (1) don't care clk cke command dqm0-dqm3 a0-a9, a11 a10 ba0, ba1 dq t ch t cl t ck t cms t cmh t cms t cmh t cms t cmh t cks t ckh t0 t1 tn+1 t o+1 tp+1 tp+2 tp+3 t mrd t rc t rc t rp ro w ro w bank t as t ah t as t ah code code all banks single bank all banks au to refresh au to refresh load mode register t = 100s min. po wer-up: v cc and clk stab le precharge all banks au to refresh program mode register nop precharge nop nop nop a ctive t (2, 3, 4) au to refresh code t as t ah notes: 1. if cs is high at clock high time, all commands applied are nop. 2. the mode register may be loaded prior to the auto-refresh cycles if desired. 3. jedec and pc100 specify three clocks. 4. outputs are guaranteed high-z after the command is issued.
20 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g auto-refresh cycle notes: 1. cas latency = 2, 3 t rp t rc t rc don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t as t ah t ch t cl t ck t cms t cmh t cks t ckh t0 t1 t2 tn+1 to +1 all banks single bank bank (s) ro w ro w bank high-z precharge nop nop nop a ctive au to refresh au to refresh
21 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g self-refresh cycle clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t as t ah bank t cl t ch t ck t cms t cmh t cks t ckh all banks single bank t cks precharge all activ e banks clk stab le pr ior to e xiting self refresh mode enter self refresh mode exit self refresh mode (restar t refresh time base) t0 t1 t2 tn+1 to +1 to +2 high-z au to refresh au to refresh precharge nop nop nop t cks t ras t rp t xsr don't care note: 1. self-refresh mode is not supported for a2 grade with t a > +85 o c.
22 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g register definition mode register the mode register is used to defne the specifc mode of operation of the sdram. this defnition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in mode register definition. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifes the type of burst (sequential or interleaved) , m4- m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifes the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specifed time before initiating the subsequent operation. violating either of these requirements will result in unspecifed operation. mode register definition latency mode m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved 1. to ensure compatibility with future devices, should program ba1, ba0, a11, a10 = "0" write burst mode m9 mode 0 programmed burst length 1 single location access operating mode m8 m7 m6-m0 mode 0 0 defined standard operation ? ? ? all other states reserved burst type m3 type 0 sequential 1 interleaved burst length m2 m1 m0 m 3=0 m3=1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved reserved address bus mode register (mx) (1) ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
23 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a8 cn, cn + 1, cn + 2 not supported page cn + 3, cn + 4... (y) (location 0-y) cn - 1, cn burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in mode register definition. the burst length deter - mines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean - ing that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a8 (x32) when the burst length is set to two; by a2-a8 (x32) when the burst length is set to four; and by a3-a8 (x32) when the burst length is set to eight. the remaining (least signifcant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definition table.
24 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care undefined clk command dq read nop nop nop cas latency - 3 t ac t oh d out t0 t1 t2 t3 t4 t lz clk command dq read nop nop cas latency - 2 t ac t oh d out t0 t1 t2 t3 t lz cas latency cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the frst piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. the dqs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in cas latency diagrams. the allowable operating frequency table indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. cas latency allowable operating frequency (mhz) speed cas latency = 2 cas latency = 3 -5 100 200 -6 100 166 -7 133 143 operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used be - cause unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses.
25 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g clk cke row address bank address cs ras cas we a0-a11 ba0, ba1 high activating specific row within spe - cific bank don't care clk command ac tive nop nop t rcd t0 t1 t2 t3 t4 read or write chip operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be opened. this is accomplished via the active command, which selects both the bank and the row to be activated (see activating specifc row within specifc bank ). after opening a row (issuing an active command) , a read or write command may be issued to that row, subject to the t rcd specifcation. minimum t rcd should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specifcation of 18ns with a 125 mhz clock (8ns period) results in 2.25 clocks, rounded to 3. this is refected in the following example, which cov - ers any case where 2 < [t rcd (min)/t ck ] 3. (the same procedure is used to convert other specifcation limits from time units to clock cycles). a subsequent active command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). the minimum time interval between successive active commands to the same bank is defned by t rc . a subsequent active command to another bank can be issued while the frst bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defned by t rrd . example: meeting t rcd (min) when 2 < [t rcd (min)/tck] 3
26 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g clk cke high column address auto precharge no precharge cs ras cas we a0-a8 a10 ba0, ba1 bank address a9, a11 read command reads read bursts are initiated with a read command, as shown in the read command diagram. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic read commands used in the fol - lowing illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. the cas latency diagram shows general timing for each possible cas latency setting. upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncated with a sub - sequent read command, and data from a fxed-length read burst may be immediately followed by data from a read command. in either case, a continuous fow of data can be maintained. the frst data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in consecutive read bursts for cas latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architec - ture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in random read accesses, or each subsequent read may be performed to a different bank. data from any read burst may be truncated with a sub - sequent write command, and data from a fxed-length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge im - mediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be a pos - sibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figures rw1 and rw2. the dqm signal must be as - serted (high) at least three clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 in figure rw2, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. a fxed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated) , and a full-page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in the read to precharge
27 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g diagram for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fxed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fxed-length burst with auto precharge. the disadvantage of the pre - charge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fxed-length or full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fxed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in the read burst termination diagram for each possible cas latency; data element n + 3 is the last desired data element of a longer burst.
28 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk dqm command address dq t0 t1 t2 t3 t4 t5 read nop nop nop nop write bank, col n bank, col b d out n d in b t ds t hz cas latency - 3 rw1 - read to write rw2 - read to write don't care clk dqm command address dq t0 t1 t2 t3 t4 t5 t6 read nop nop nop nop nop write bank, col n d in b t ds t hz bank, col b cas latency - 2 d out n d out n+1 d out n+2
29 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 read nop nop nop read nop nop d out n d out n+1 d out n+2 d out n+3 d out b bank, col n bank, col b cas latency - 2 don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 t7 read nop nop nop read nop nop nop d out n d out n+1 d out n+2 d out n+3 d out b bank, col n bank, col b cas latency - 3 consecutive read bursts
30 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk command address dq t0 t1 t2 t3 t4 t5 read read read read nop nop d out n d out b d out m d out x bank, col n bank, col b cas latency - 2 bank, col m bank, col x don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 read read read read nop nop nop d out n d out b d out m d out x bank, col n bank, col b cas latency - 3 bank, col m bank, col x random read accesses
31 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 read nop nop nop nop nop d out n d out n+1 d out n+2 d out n+3 bank a, col n cas latency - 2 x = 1 cycle b urst termina te don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 t7 read nop nop nop nop nop nop d out n d out n+1 d out n+2 d out n+3 bank, col n cas latency - 3 x = 2 cycles burs t termina te read burst termination
32 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g alternating bank read accesses notes: 1) cas latency = 2, burst length = 4 2) x32: a9, a11 = "don't care" bank 0 bank 3 bank 3 bank 0 don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t rcd - bank 0 cas latency - bank 0 t rcd - bank 0 t ras - bank 0 t rc - bank 0 t ch t cl t ck t cms t cmh t cks t ckh a ctive nop read nop ac tive nop read nop a ctive ro w ro w bank 0 ro w ro w t rrd t rcd - bank 3 t rp - bank 0 column m (2) ro w column b (2) ro w enable au to precharge enable au to precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t ac t oh t oh t oh t oh t oh d out m d out m+ 1 d out m+ 2 d out m+ 3 d out b t ac t ac t ac t ac t ac t lz cas latency - bank 3
33 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g read - full-page burst notes: 1) cas latency = 2, burst length = full page 2) x32: a9, a11 = "don't care" don't care undefined clk cke command dqm0 - dqm 3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop read nop nop nop nop nop burst term nop nop t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd cas latency t ac t ac t ac t ac t ac t hz t lz t ac t oh t oh t oh t oh t oh t oh d out m d out m+ 1 d out m+ 2 d out m- 1 d out m d out m+ 1 each ro w (x4) has 1,024 locations full page completion full-page b urst not self-ter minating. use burst termina te command. t0 t1 t2 t3 t4 t5 t6 tn+1 tn+2 tn+3 tn+4
34 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g read - dqm operation don't care undefined clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh ac tive nop read nop nop nop nop nop nop t as t ah t as t ah t as t ah enable au to precharge disable au to precharge ro w ro w bank t rcd cas latency d out m d out m+ 2 d out m+ 3 column m (2) bank t ch t cl t ck t cms t cmh t cks t ckh t oh t oh t oh t ac t ac t ac t hz t hz t lz t lz t0 t1 t2 t3 t4 t5 t6 t7 t8 notes: 1) cas latency = 2, burst length = 4 2) x32: a9, a11 = "don't care"
35 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 t7 read nop nop nop nop ac tive nop d out n d out n+1 d out n+2 d out n+3 bank a, col n bank a, ro w bank (a or all) cas latency - 2 t rp precharge t rql high-z don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 t7 read nop nop nop nop nop ac tive d out n d out n+1 d out n+2 d out n+3 bank, col n bank, col b cas latency - 3 t rp t rql bank a, ro w precharge high-z read to precharge
36 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g clk cke high column address auto precharge bank address cs ras cas we a0-a8 a10 ba0, ba1 no precharge a9, a11 write command the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the frst valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive posi - tive clock edge. upon completion of a fxed-length burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see write burst). a full-page burst will con - tinue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data for any write burst may be truncated with a subse - quent write command, and data for a fxed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coincident with the new command applies to the new command. an example is shown in write to write diagram. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in random write cycles, or each subsequent write may be performed to a different bank. data for any write burst may be truncated with a subse - quent read command, and data for a fxed-length write burst may be immediately followed by a subsequent read command. once the read com mand is registered, the data inputs will be ignored, and writes will not be ex - ecuted. an example is shown in write to read. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fxed-length write burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not acti - vated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t dpl after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t dpl of at least one clock plus time, regardless of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in the write to pre - charge diagram. data n +1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fxed-length burst being executed to comple - tion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fxed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fxed-length or full-page bursts. fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncat - ing a write burst, the input data applied coincident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in write burst termination, where data n is the last desired data element of a longer burst. writes write bursts are initiated with a write command, as shown in write command diagram.
37 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g clk command address dq t0 t1 t2 t3 write nop nop nop d in n d in n+1 bank, col n don't care clk command address dq t0 t1 t2 write nop write d in n d in n+1 d in b bank, col n bank, col b don't care write burst write to write clk command address dq t0 t1 t2 t3 write write write write d in n d in b d in m d in x bank, col n bank, col b bank, col m bank, col x random write cycles
38 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk command address dq t0 t1 t2 t3 t4 t5 write nop read nop nop nop d in n d in n+1 d out b d out b+1 bank, col n bank, col b cas latency - 2 write to read wp1 - write to precharge don't care clk dqm command address dq t0 t1 t2 t3 t4 t5 t6 write nop nop nop ac tive nop bank a, col n bank a, ro w bank (a or all) t dpl t rp precharge d in n d in n+1 d in n+2
39 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g clk command address dq t0 t1 t2 write d in n (d ata ) bank, col n don't care ( address) burs t terminat e next command write burst termination don't care clk dqm command address dq t0 t1 t2 t3 t4 t5 t6 write nop nop nop nop a ctive bank a, col n bank a, ro w bank (a or all) t dpl t rp precharge d in n d in n+1 wp2 - write to precharge
40 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop write nop nop nop nop burst term nop t as t ah t as t ah t as t ah t ds t dh t ds t dh t ds t dh ro w ro w bank t rcd d in m d in m+ 1 d in m+ 2 d in m+ 3 d in m- 1 column m (2) t ch t cl t ck t ds t dh t ds t dh t ds t dh t cms t cmh t cks t ckh bank full page completed t0 t1 t2 t3 t4 t5 tn+1 tn+2 write - full page burst notes: 1) burst length = full page 2) x32: a9, a11 = "don't care"
41 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh ac tive nop write nop nop nop nop nop t as t ah t as t ah t as t ah t ds t dh t ds t dh t ds t dh enable au to precharge disable au to precharge ro w ro w bank t rcd d in m d in m+ 2 d in m+ 3 column m (2) bank t ch t cl t ck t cms t cmh t cks t ckh t0 t1 t2 t3 t4 t5 t6 t7 write - dqm operation notes: 1) burst length = 4 2) x32: a9, a11 = "don't care"
42 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g alternating bank write accesses bank 0 bank 1 bank 1 bank 0 don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t ds t dh t ds t dh t ds t dh t rcd - bank 0 t rcd - bank 0 t dpl - bank 1 t ras - bank 0 t rc - bank 0 t ch t cl t ck t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t cms t cmh t cks t ckh a ctive nop write nop ac tive nop write nop nop a ctive d in m d in m+ 1 d in m+ 2 d in m+ 3 d in b d in b+ 1 d in b+ 2 d in b+ 3 ro w ro w bank 0 ro w ro w t rrd t rcd - bank 1 t dpl - bank 0 t rp - bank 0 column m (2) ro w column b (2) ro w enable au to precharge enable au to precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 notes: 1) burst length = 4 2) x32: a9, a11 = "don't care"
43 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk cke command address dq t0 t1 t2 t3 t4 t5 nop write nop nop bank a, col n d in n d in n+1 d in n+2 internal clock don't care clk cke command address dq t0 t1 t2 t3 t4 t5 t6 read nop nop nop nop nop bank a, col n d out n d out n+1 d out n+2 d out n+3 internal clock clock suspend clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, freezing the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see following examples.) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. clock suspend during write burst clock suspend during read burst
44 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g clock suspend mode notes: 1) cas latency = 3, burst length = 2, auto precharge is disabled. 2) x32: a9, a11 = "don't care" don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t ch t cl t ck t cms t cmh t cks t ckh column m (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 read nop nop nop nop nop write nop t cks t ckh bank bank column n (2) t ac t ac t oh t hz d out m d out m+1 t lz undefined d in e+1 t ds t dh d in e
45 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g clk cke high all banks bank select bank address cs ras cas we a0-a9, a11 a10 ba0, ba1 don't care clk cke command nop nop a ctive t cks t cks all banks idle enter po wer-do wn mode exit po wer-do wn mode t rcd t ras t rc input b uff ers gated off less than t ref precharge command power-down power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cks ). see fgure below (power-down). precharge the precharge command (see fgure) is used to deac - tivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specifed time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank.
46 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g power-down mode cycle don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t as t ah bank t ch t cl t ck t cms t cmh t cks t ckh precharge nop nop nop ac tive all banks single bank ro w ro w bank t cks t cks precharge all activ e banks all banks idle tw o cloc k cycles input b uff ers gated off while in po wer-do wn mode all banks idle , enter po wer-do wn mode exit po wer-do wn mode t0 t1 t2 tn+1 tn+2 high-z note: x32: a9, a11 = "don't care"
47 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk command bank n bank m address dq t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop d out a d out a+1 d out b d out b+1 bank n, col a cas latency - 3 (bank n) cas latency - 3 (bank m) t rp - bank n t rp - bank m read - ap bank n read - ap bank m pa ge activ e read with burst of 4 interr upt burst, precharge idle pa ge activ e read with burst of 4 precharge inter nal states bank n, col b don't care clk command bank n bank m address dqm dq t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop d out a d in b d in b+1 d in b+2 d in b+3 bank n, col a bank m, col b cas latency - 3 (bank n) t rp - bank n t dpl - bank m read - ap bank n write - ap bank m read with burst of 4 interr upt burst, precharge idle pa ge activ e write with burst of 4 wr ite-bac k inter nal states p age activ e burst read/single write the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). concurrent auto precharge an access command (read or write) to another bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. issi sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defned below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered. 2. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used three clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered. read with auto precharge interrupted by a read read with auto precharge interrupted by a write
48 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g don't care clk command bank n bank m address dq t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop d in a d in a+1 d out b d out b+1 bank n, col a bank m, col b cas latency - 3 (bank m) t rp - bank n t rp - bank m write - ap bank n read - ap bank m pa ge activ e write with burst of 4 interr upt burst, wr ite-bac k precharge pa ge activ e read with burst of 4 precharge inter nal states t dpl - bank n don't care clk command bank n bank m address dq t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop bank n, col a bank m, col b t rp - bank n t dpl - bank m write - ap bank n write - ap bank m pa ge activ e write with burst of 4 interr upt burst, wr ite-bac k precharge pa ge activ e write with burst of 4 wr ite-bac k inter nal states t dpl - bank n d in a d in a+1 d in a+2 d in b d in b+1 d in b+2 d in b+3 write with auto precharge 3. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a write on bank n when registered, with the data-out appearing (cas latency) later. the precharge to bank n will begin after t dpl is met, where t dpl begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 4. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t dpl is met, where t dpl begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m. write with auto precharge interrupted by a read write with auto precharge interrupted by a write
49 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g single read without auto precharge don't care undefined clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop read nop nop precharge nop a ctive nop t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd t ras t rc cas latency t ac t hz t oh d out m t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp disable au to precharge ro w ro w bank t lz all banks single bank bank notes: 1) cas latency = 2, burst length = 1 2) x32: a9, a11 = "don't care"
50 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g single read with auto precharge don't care undefined clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop nop nop read nop nop a ctive nop t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd t ras t rc cas latency t ac t hz t oh d out m t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp enable au to precharge ro w ro w bank notes: 1) cas latency = 2, burst length = 1 2) x32: a9, a11 = "don't care"
51 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g read without auto precharge don't care undefined clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop read nop nop nop precharge nop ac tive t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd cas latency t ac t ac t ac t ac t oh t hz t oh d out m t oh d out m+1 t oh d out m+2 d out m+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 disable au to precharge ro w ro w bank t lz t ras t rc t rp all banks single bank bank notes: 1) cas latency = 2, burst length = 4 2) x32: a9, a11 = "don't care"
52 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g read with auto precharge don't care undefined clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop read nop nop nop nop nop ac tive t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd t ras t rc cas latency t ac t ac t ac t ac t oh t hz t oh d out m t oh d out m+1 t oh d out m+2 d out m+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp enable au to precharge ro w ro w bank t lz notes: 1) cas latency = 2, burst length = 4 2) x32: a9, a11 = "don't care"
53 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g single write - without auto precharge don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t ds t dh t rcd t ras t rc t ch t cl t ck t cms t cmh t cks t ckh a ctive nop write nop nop precharge nop ac tive nop t dpl (3) t rp ro w ro w ro w bank d in m column m (2) ro w bank bank bank all banks single bank t0 t1 t2 t3 t4 t5 t6 t7 t8 disable au to precharge notes: 1) burst length = 1 2) x32: a9, a11 = "don't care" 3) t ras must not be violated.
54 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g single write with auto precharge notes: 1) burst length = 1 2) x32: a9, a11 = "don't care" don't care clk cke command dqm0-dqm 3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t ds t dh t rcd t ras t rc t ch t cl t ck t cms t cmh t cks t ckh a ctive nop nop nop write nop nop nop ac tive nop t dpl t rp column m (2) ro w bank bank enable au to precharge ro w ro w ro w bank d in m t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
55 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g write - without auto precharge don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t rcd t ras t rc t ch t cl t ck t cms t cmh t cks t ckh a ctive nop write nop nop nop precharge nop a ctive t dpl (3) t rp column m (2) ro w disable au to precharge ro w ro w ro w bank t ds t dh t ds t dh t ds t dh t ds t dh d in m d in m+ 1 d in m+ 2 d in m+ 3 bank bank bank all banks single bank t0 t1 t2 t3 t4 t5 t6 t7 t8 notes: 1) burst length = 4 2) x32: a9, a11 = "don't care" 3) t ras must not be violated.
56 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g write - with auto precharge don't care clk cke command dqm0 - dqm3 a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t rcd t ras t rc t ch t cl t ck t cms t cmh t cks t ckh a ctive nop write nop nop nop nop nop nop ac tive t dpl t rp column m (2) ro w bank bank enable au to precharge ro w ro w ro w bank t ds t dh t ds t dh t ds t dh t ds t dh d in m d in m+ 1 d in m+ 2 d in m+ 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 notes: 1) burst length = 4 2) x32: a9, a11 = "don't care"
57 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g automotive range: -40 c to +85 c frequency speed (ns) order part no. package 166 mhz 6 is45s32800g-6bla1 90-ball tf-bga, lead-free 143 mhz 7 is45s32800g-7ba1 90-ball tf-bga 143 mhz 7 is45s32800g-7bla1 90-ball tf-bga, lead-free automotive range: -40 c to +105 c frequency speed (ns) order part no. package 143 mhz 7 is45s32800g-7bla2 90-ball tf-bga, lead-free *contact issi for leaded part support. ordering information - vdd = 3.3v commercial range: 0c to +70c frequency speed (ns) order part no. package 166 mhz 6 IS42S32800G-6B 90-ball tf-bga 166 mhz 6 IS42S32800G-6Bl 90-ball tf-bga, lead-free 143 mhz 7 is42s32800g-7b 90-ball tf-bga 143 mhz 7 is42s32800g-7bl 90-ball tf-bga, lead-free industrial range: -40c to +85c frequency speed (ns) order part no. package 166 mhz 6 IS42S32800G-6Bi 90-ball tf-bga 166 mhz 6 IS42S32800G-6Bli 90-ball tf-bga, lead-free 143 mhz 7 is42s32800g-7bi 90-ball tf-bga 143 mhz 7 is42s32800g-7bli 90-ball tf-bga, lead-free
58 integrated silicon solution, inc . - www.issi.com rev. a 07/18/2012 is42s32800g, is45s32800g 0.45 0.80 d 1 2. reference document : jedec mo-207 1. controlling dimension : mm . note : package outline 08/14/2008

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